In a wireless communications system such as an orthogonal frequency domain multiplexing (OFDM) communications system, the reference clock in the receiver will not in general be common to that of the transmitter. As a consequence, in a sampled system, the transmitter digital-to-analog converter (DAC) sample rate and the receiver analog-to-digital converter (ADC) sample rate will both have arbitrary sampling phase and period. Any error in the reference clocks used to derive the sampling frequency in either or both of the transmitter and receiver will introduce an offset in the sampling frequency at the receiver, which is referred to herein as Sample Frequency Offset (SFO).
With a relatively narrow-band system, or with a low order fast Fourier transform (FFT), the effect of SFO during the block of data (e.g. an OFDM symbol) presented to the FFT is typically not problematic. A drift in sampling time will be apparent and can be corrected post FFT as a phase slope across output FFT bins (i.e. sub-carriers or tones). This drift can be tracked and corrected post FFT during continued reception. This only corrects the SFO on the total sample drift over, for example, an OFDM symbol period (including Guard Interval).
Meanwhile, the present inventors have recognized that when a higher order FFT (for example ≧256 bins) is utilized, and/or higher order modulation schemes are introduced (for example 256QAM), a secondary source of inter-carrier interference (ICI) post FFT becomes increasingly significant. This can be viewed in a number of ways but most simply the sampling point in the receiver is continually drifting compared to that in the transmitter. This drift (or changing phase slope post FFT) will result in an increasing (with distance in frequency from DC) effective subcarrier frequency offset, which further results in a non-flat noise floor post FFT due to ICI.
Conventionally, a possible approach to address such problems in a digital receiver would be to incorporate a resampler in the system before the boundaries of the data block are known. This approach requires a complex design in order to accurately interpolate over all sample timing errors. All sample phases have to be corrected during continued reception. This approach also causes significant issues with feeding back the estimated SFO which may not be known when the data samples are processed by the resampler.
Alternatively, the SFO induced ICI can be ignored. However, this is only a viable option for receivers with low order FFTs, relatively low maximum SFO and lower order modulation (and for example no MIMO). Designing a system which utilizes the latter approach for narrow bandwidth modes of operation and a continuous resampler for wider bandwidth modes is neither desirable nor an efficient use of hardware resources.
As another possible alternative, the sample clock itself can be controlled. However, this approach inherently introduces the complexity of feedback to the analog domain, delay (and uncertainty when it is applied) in the correction and issues with accuracy of control.
Accordingly, there is a need in the art for solutions to these and other problems.